The present invention relates to a memory device; and, more particularly, to a memory device capable of improving a characteristic of a bit line precharge time tRP.
In general, a dynamic random access memory (DRAM), one type of semiconductor memory device, selects a specific memory cell through a row decoder, and writes/reads data to/from the selected specific memory cell through bit lines. A bit line sense amplifier (BLSA) coupled to the bit lines amplifies the data.
FIG. 1 is a block diagram showing the structure of a conventional semiconductor memory device having a bit line sense amplifier. One cell array block shares two bit line sense amplifiers.
Referring to FIG. 1, a plurality of cell array blocks BLOCK0 to BLOCKN are shared by one column decoder YDEC, and each cell array block is shared by two bit line sense amplifiers BLSA.
Here, the cell array blocks BLOCK0 to BLOCKN are arrayed at positions corresponding to a word line (WL) and a bit line (BL), and are constituted by a cell array having a plurality of memory cells for storing the data. The bit line sense amplifier BLSA includes edge bit line sense amplifiers BLSA_EDGE and central bit line sense amplifiers BLSA. The edge bit line sense amplifiers BLSA_EDGE are disposed at the highest cell array block BLOCK0 and the lowest cell array block BLOCKN, and the central bit line sense amplifiers BLSA are disposed between the cell array blocks.
In other words, while the central bit line sense amplifiers BLSA are disposed between the cell array blocks, the edge bit line sense amplifiers BLSA_EDGE are coupled only to the highest cell array block BLOCK0 and the lowest cell array block BLOCKN in which there is no cell at one side thereof.
FIG. 2 is a circuit diagram showing the edge bit line sense amplifier BLSA_EDGE, a bit line control block containing peripheral circuits, and a cell array block according to the prior art. In the case where bit lines BL0 and /BL0 are precharged after the activation of word line WL0 of the top cell array block BLOCK0, the operation of the bit line sense amplifier will be described with reference to FIG. 2.
Referring to FIG. 2, the conventional edge bit line sense amplifier and control circuits include a cell array block 10, a sense amplifier 20, a precharge unit 30, a block selection unit 40 and an equalization unit 50.
The cell array block 10 is arrayed at a position corresponding to a word line WL0 and a bit line pair BL0 and /BL0, and is provided with a plurality of memory cell arrays for storing the cell data. The sense amplifier 20 senses and amplifies the cell data through the bit line pair BL0 and /BL0 coupled to the cell array block 10.
The precharge unit 30 precharges the bit line pair BL and /BL0 to a predetermined potential level in response to a bit line precharge control signal BLPG_0. The block selection unit 40 controls the connection between the block 10 and the sense amplifier 20 through the bit line pair BL0 and /BL0 in response to a bit line isolation signal BISL_0.
The equalization unit 50 is coupled between the block selection unit 40 and the cell array block 10, and directly equalizes the bit line pair BL0 and /BL0 in response to a bit line equalization signal BLEQL_0.
Here, the precharge unit 30 includes a bit line precharge voltage applying terminal VBLP, a first NMOS transistor N1 and a second NMOS transistor N2. A predetermined potential level, generally half the power supply voltage level (that is, Vcc/2), is applied to the bit line precharge voltage applying terminal VBLP. The bit line precharge control signal BLPG_0 is commonly applied to each gate of the first and the second NMOS transistors N1 and N2.
The block selection unit 40 includes a third NMOS transistor N3 and a fourth NMOS transistor N4, which are coupled to the bit line pair BL0 and /BL0, respectively. The bit line isolation signal BISL_0 is commonly applied to each gate of the third and the fourth NMOS transistors N3 and N4.
The equalization unit 50 includes a fifth NMOS transistor N5 having a gate receiving the bit line equalization signal BLEQL_0, and a source and a drain coupled between the bit line pair BL0 and /BL0.
Meanwhile, the bit line precharge control signal BLPG_0 is a signal that is activated when the bit line pair BL0 and /BL0 are precharged. That is, the bit line precharge control signal BLPG_0 is enabled from a low level to a high level when the bit line pair BL0 and /BL0 are precharged.
The bit line isolation signal BISL0 is a signal that is activated to a high level in order to select a lower cell array block among a plurality of blocks. That is, the bit line isolation signal BISL_0 maintains a predetermined level Vpp higher than the power supply voltage level Vcc at the activation operation and is set to the power supply voltage level Vcc in the precharge operation.
The bit line equalization signal BLEQL_0 is a signal that is activated in order to equalize the bit lines to a predetermined potential level. That is, the bit line equalization signal BLEQL_0 is enabled from a low level to a high level at the precharge operation of the bit line pair BL0 and /BL0.
Referring to FIG. 2, the bit line precharge control signal BLPG_0 is enabled from the low level to the high level at the precharge operation of the bit lines, so that the first and the second NMOS transistors N1 and N2 are turned on. In response to the first and the second NMOS transistors N1 and N2 being turned on, the bit line pair BL0 and /BL0 are set to the bit line precharge voltage (VBLP) level, which is typically half the power supply voltage level Vcc.
At this time, the bit line isolation signal BISL_0 maintains the predetermined level Vpp higher than the power supply voltage level Vcc at the activation operation of the bit lines and is set to the power supply voltage level Vcc in the precharge operation thereof, so that the third and the fourth NMOS transistors N3 and N4 are maintained at a turned-on state. Also, the bit line equalization signal BLEQL_0 is enabled from the low level to the high level in the precharge operation of the bit line pair BL0 and /BL0, so that the fifth NMOS transistor N5 is turned on.
As described above, when the bit line pair BL0 and /BL0 disposed at the edge portion (hereinafter, referred to as an edge bit line pair) are precharged, the first, the second and the fifth NMOS transistors N1, N2 and N5 are turned on, and the third and the fourth NMOS transistors N3 and N4 are maintained at a turned-on state.
FIG. 3 is a circuit diagram showing a central bit line sense amplifier and peripheral circuits, in which one bit line sense amplifier is shared with two cell array blocks. In FIG. 3, for the sake of convenience, only two cell array blocks (a top cell array block 10 and a bottom cell array block 11) are illustrated.
Referring to FIG. 3, the central bit line sense amplifier and peripheral circuits include top and bottom cell array blocks 10 and 11, a sense amplifier 21, a precharge unit 31, a top cell array block selection unit 41a, a top cell array block equalization unit 51a, a bottom cell array block selection unit 41b and a bottom cell array block equalization unit 51b. 
The top and the bottom cell array blocks 10 and 11 are arrayed at positions corresponding to a word line and a bit line pair, and are provided with a plurality of memory cell arrays for storing the cell data.
The sense amplifier 21 senses and amplifies the cell data through the bit line pair BL1 and /BL1 commonly coupled to the top and bottom cell array blocks 10 and 11.
The precharge unit 31 precharges the bit line pair BL1 and /BL1 to a predetermined potential level in response to a bit line precharge control signal BLPG_1.
The top cell array block selection unit 41a controls a connection between the top cell array block 10 and the sense amplifier 21 through the bit line pair BL1 and /BL1 in response to a bit line isolation signal BISH_1.
The top cell array block equalization unit 51a is coupled between the top cell array block selection unit 41a and the top cell array block 10, and equalizes the bit line pair BL1 and /BL1 disposed in the direction of the top block 10 in response to a bit line equalization signal BLEQH_1.
The bottom cell array block selection unit 41b controls a connection between the bottom cell array block 11 and the sense amplifier 21 through the bit line pair BL1 and /BL1 in response to a bit line isolation signal BISL_1.
The bottom cell array block equalization unit 51b is coupled between the bottom cell array block selection unit 41b and the bottom cell array block 11, and equalizes the bit line pair BL1 and /BL1 disposed in the direction of the bottom cell array block 11 in response to a bit line equalization signal BLEQL_1.
Here, the precharge unit 31 includes a bit line precharge voltage applying terminal VBLP to which a predetermined potential level is applied, a ninth NMOS transistor N9 and a tenth NMOS transistor N10. A bit line precharge control signal BLPG_1 is commonly applied to each gate of the ninth and the tenth NMOS transistors N9 and N10.
The top cell array block selection unit 41a includes a seventh NMOS transistor N7 and an eighth NMOS transistor N8. The bit line isolation signal BISH_1 is commonly applied to each gate of the seventh and the eighth NMOS transistors N7 and N8.
The top cell array block equalization unit 51a includes a sixth NMOS transistor N6 having a gate receiving the bit line equalization signal BLEQH_1.
The bottom cell array block selection unit 41b includes an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12, each gate of which commonly receives the bit line isolation signal BISL_1.
The bottom cell array block equalization unit 51b includes a thirteenth NMOS transistor N13 whose gate receives the bit line equalization signal BLEQL_1.
Meanwhile, the bit line precharge control signal BLPG_1 is a signal that is enabled from a low level to a high level in the precharge operation of the bit line pair BL1 and /BL1.
The bit line isolation signals BISH_1 and BISL_1 are signals that maintain predetermined levels Vpp greater than the power supply voltage level Vcc in the activation operation of the bit line pair BL1 and /BL1 and are then set to the power supply voltage level Vcc at the precharge operation thereof. The bit line isolation signal BISH_1 used for isolating the top cell array block 10 from the sense amplifier 21 is set to the predetermined level Vpp at the activation of the word line WL0 and is set to the power supply voltage level Vcc in the precharge operation. If the cell data are read out from the bottom cell array block 11, not the top cell array block 10, isolation is not needed, so that the bit line isolation signal BISH_1 is set to the low level.
Also, the bit line isolation signal BISH_1 is a signal that is enabled to the power supply voltage level at the activation of the word line WL0, and the bit line isolation signal BISL_1 is a signal that is set to the power supply voltage level at the precharge operation in order to isolate the bottom cell array block 11 from the bit line sense amplifier 21.
The bit line equalization signals BLEQH_1 and BLEQL_1 are signals that are activated to the high level in order to equalize the bit line pair BL1 and /BL1 to a predetermined potential level. That is, the bit line equalization signal BLEQH_1 is enabled to the high level in order to equalize the bit lines disposed in the direction of the top cell array block 10 at the precharge operation, and the bit line equalization signal BLEQL_1 is enabled to the high level in order to equalize the bit lines disposed in the direction of the bottom cell array block 11.
Referring to FIG. 3, in the precharge operation, the bit line equalization signals BLEQH_1 and BLEQL_1 are enabled from the low level to the high level, and the bit line isolation signals BISH_1 and BISL_1 are set to the power supply voltage level Vcc. Additionally, the bit line precharge control signal BLPG_1 is enabled from the low level to the high level, so that the bit line pair BL1 and /BL1 are shorted to the bit line precharge voltage (VBLP) level. Consequently, the bit line pair BL1 and /BL1 are precharged.
As shown in FIG. 3, the precharge operation of the bit line pair BL1 and /BL1 disposed at the central portion (hereinafter, referred to as a central bit line pair) is performed through eight NMOS transistors N6 to N13.
FIG. 4 is a circuit diagram of the conventional memory device, showing the precharge operation of the central and edge bit line pairs carried out by disabling the word line WL0 of the top cell array block.
Referring to FIG. 4, the conventional memory device includes a plurality of cell array blocks 10 and 11 and a bit line control block 210 and 220. The bit line control block includes a first control block 210 and a second control block 220.
The cell array blocks 10 and 11 are provided with a plurality of memory cells operating according to signals of word lines WL0 and WL1, a first bit line pair BL0 and /BL0 and a second bit line pair BL1 and /BL1.
The first control block 210 is separately coupled to the first bit line pair BL0 and /BL0 which are coupled to the top cell array block 10 among the cell array blocks, and the second control block 220 is shared with the second bit line pair BL1 and /BL1 which are coupled between the top cell array block 10 and the bottom cell array block 11.
The first control block 210 also includes an edge sense amplifier 20, a precharge unit 30, a cell array block selection unit 40 and an equalization unit 50.
The edge sense amplifier 20 senses the cell data stored in the memory cell of the top cell array block 10 through the first bit line pair BL0 and /BL0. The precharge unit 30 is coupled between the edge sense amplifier 20 and an end portion of the first bit line pair BL0 and /BL0, and precharges the first bit line pair BL0 and /BL0 to a predetermined level VBLP1 in response to a bit line precharge control signal BLPG_0.
The cell array block selection unit 40 controls a connection between the top cell array block 10 and the edge sense amplifier 20 in response to a bit line isolation signal BISL_0. The equalization unit 50 is coupled between the cell array block selection unit 40 and the top cell array block 10, and equalizes the first bit line pair BL0 and /BL0 in response to a bit line equalization signal BLEQL_0.
The second block 220 also includes a central sense amplifier 21, a precharge unit 31, a first cell array block selection unit 41a, a first equalization unit 51a, a second cell array block selection unit 41b and a second equalization unit 51b. 
The central sense amplifier 21 senses the cell data stored in the memory cell of the top and bottom cell array blocks 10 and 11 through the second bit line pair BL1 and /BL1 coupled to the top cell array block 10 and the bottom cell array block 11.
The precharge unit 31 is coupled between the central sense amplifier 21 and the top cell array block 10, and precharges the second bit line pair BL1 and /BL1 to a predetermined level VBLP1 in response to a bit line precharge control signal BLPG_1.
The first cell array block selection unit 41a controls a connection between the top cell array block 10 and the central sense amplifier 21 in response to a first bit line isolation signal BISH_1. The first equalization unit 51a is coupled between the first cell array block selection unit 41a and the top cell array block 10, and equalizes the second bit line isolation signal BL1 and /BL1 in response to a first bit line equalization signal BLEQH_1.
The second cell array block selection unit 41b controls a connection between the bottom cell array block 11 and the central sense amplifier 21 in response to a second bit line isolation signal BISL_1. The second equalization unit 51b is coupled between the second cell block selection unit 41b and the bottom cell array block 11, and equalizes the second bit line pair BL1 and /BL1 in response to a second bit line equalization signal BLEQL_1.
Meanwhile, the precharge units 30 and 31 contained in the first and the second control blocks 210 and 220 also include bit line precharge voltage applying terminals VBLP1 and NMOS transistors N1 and N2, N9 and N10, respectively. The bit line precharge control signal BLPG_0 is commonly applied to each gate of the NMOS transistors N1 and N2, and the bit line precharge control signal BLPG_1 is commonly applied to each gate of the NMOS transistors N9 and N10.
The cell array block selection units 40, 41a and 41b are implemented with NMOS transistors N3 and N4, N7 and N8, N11 and N12, each of whose gates commonly receives the bit line isolation signals BISL_0, BISH_1 and BISL_1, respectively.
Also, the equalization units 50, 51a and 51b are implemented with NMOS transistors N5, N6, N13, each of whose gates receives the bit line equalization signals BLEQL_0, BLEQH_1 and BLEQL_1, respectively.
Here, the bit line precharge control signal BLPG_0 is a signal that is activated in the precharge operation of the bit lines. That is, the bit line precharge control signal BLPG_0 is enabled from a low level to a high level when the first bit line pair BL0 and /BL0 are precharged, and the bit line precharge control signal BLPG_1 is enabled from a low level to a high level when the second bit line pair BL1 and /BL1 are precharged.
The bit line isolation signals BISL and BISH are used to select the bottom cell array block and the top cell array block, respectively. That is, the bit line isolation signals BISL_0, BISL_1 and BISH_1 are maintained at a predetermined level Vpp higher than the power supply voltage level Vcc at the activation operation and are set to the power supply voltage level Vcc when the first and the second bit line pairs BL0, /BL0, BL1 and /BL1 are precharged.
The bit line equalization signal BLEQL_0 is a signal that is activated to equalize the bit lines to a predetermined potential level. That is, the bit line equalization signal BLEQL_0 is enabled from a low level to a high level at the precharge operation of the first bit line pair BL0 and /BL0.
Referring to FIG. 4, when the first bit line pair BL0 and /BL0 and the second bit line pair BL1 and /BL1 are precharged, the bit lines BL1 and /BL1 of the central sense amplifier 21 disposed between the top cell array block 10 and the bottom cell array block 11 are precharged through eight NMOS transistors N6 to N13. Meanwhile, the bit lines BL0 and /BL0 of the edge sense amplifier 20 disposed at only one block (the top cell array block) are precharged through five NMOS transistors N1 to N5.
As described above, when the bit lines are precharged, the precharge time of the edge bit lines is different from that of the central bit lines. Particularly, since the precharge speed of the edge bit lines is slowest, the characteristic of a bit line precharge time tRP is degraded.
Here, the bit line precharge time tRP is the time taken until the bit lines are again activated after a precharge command of the bit lines. If the precharge speed at the edge bit lines is different from that at the central bit lines, it causes degradation of the characteristic of the bit line precharge time tRP.
Accordingly, in order to prevent the degradation of the characteristic of the bit line precharge time tRP, a method for reducing the precharge speed difference between the edge bit lines and the central bit lines is required.
It is, therefore, an object of the present invention to provide a memory device capable of preventing a characteristic of the bit line precharge time tRP from being degraded due to a precharge speed difference between the edge bit lines and the central bit lines.
In accordance with an aspect of the present invention, there is provided a memory device comprising: a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair; a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with a second bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block; and a precharge reinforcement means, coupled to a predetermined portion of the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.
In accordance with another aspect of the present invention, there is provided a memory device comprising: a plurality of cell array blocks provided with a plurality of memory cells coupled to a word line and a bit line pair; a bit line control block including a first control block and a second control block, wherein the first control block is separately coupled to a first bit line pair coupled to a first cell array block among the cell array blocks, and the second control block is shared with the first bit line pair commonly coupled to the first cell array block and a second cell array block adjacent to the first cell array block; a precharge voltage applying terminal for providing a precharge voltage to the first bit line pair; an equalizing reinforcement means for equalizing the first bit line pair to the precharge voltage level provided from the precharge voltage applying terminal; and a precharge reinforcement means, coupled between the equalizing reinforcement means and the first control block, for reducing a precharge speed difference between the first bit line pair and the second bit line pair.